DCM使用手冊

Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs

DCMs integrate advanced clocking capabilities into the Spartan-3 global clock distribution
network. Consequently, Spartan-3 DCMs solve a variety of common clocking issues, especially
in high-performance, high frequency applications:
? Multiply or Divide an Incoming Clock Frequency or synthesize a completely new
frequency by a mixture of clock multiplication and division.
? Condition a Clock, ensuring a clean output clock with a 50% duty cycle.
? Phase Shift a clock signal, either by a fixed fraction of a clock period or by precise
increments.
? Eliminate Clock Skew, either within the device or to external components, to improve
overall system performance and to eliminate clock distribution delays.
? Mirror, Forward, or Rebuffer a Clock Signal, often to deskew and convert the incoming
clock signal to a different I/O standard—for example, forwarding and converting an
incoming LVTTL clock to LVDS.
? Any or all the above functions, simultaneously