The AD9552 is a fractional-N, phase-locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigma-delta (Σ-Δ) modulator (SDM) to accommodate fractional fre-quency synthesis. The user supplies an input reference signal by connecting a single-ended clock signal directly to the REF pin or by connecting a crystal resonator across the XTAL pins.

The AD9552 is pin programmable, providing one of 64 standard output frequencies based on one of eight common input frequencies. The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency ratios.

The AD9552 relies on an external capacitor to complete the loop filter of the PLL. The output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9552 is implemented in a strictly CMOS process.

The AD9552 is specified to operate over the extended industrial temperature range of ?40°C to +85°C.

Applications

• Cost-effective replacement for high frequency VCXO, OCXO, and SAW resonators
• Extremely flexible frequency translation with low jitter for SONET/SDH (including FEC), 10-Gigabit Ethernet, Fibre Channel, and DRFI/DOCSIS
• High definition video frequency translation
• Wireless infrastructure
• Test and measurement (including handheld devices)